Integrated circuits are interconnected networks of resistors, transistors and other electrical components that are generally formed on a silicon substrate or wafer with conductive, insulative and semiconductive materials. Fabricating integrated circuits involves forming electrical components at a number of layers and different locations. The various components are then wired or interconnected, together to form a memory or other electric circuit. Typically, the components are connected together by interlayer contact openings or vias formed through a dielectric layer to an underlying component and by conductive lines formed in trenches in the dielectric layer that extend from the via to one or more other vias in the layer. The trenches and vias are typically filled with aluminum, tungsten, copper, gold, silver, polysilicon, or other suitable conductive material.
The never-ending miniaturization of integrated circuits (Ie) is leading to denser and finer pitched chips with ever increasing speed and performance. In order to enhance the performance of advanced integrated circuits, the interconnect systems are gradually migrating from aluminum-based metallurgy to higher-conductivity and more electromigration-resistant copper.
Of the several schemes proposed for fabricating copper interconnects, the most promising method appears to be the damascene process. In a single damascene process, channels or trenches are etched into the dielectric layer, and a metal is deposited to fill the etched trenches forming an interconnect line. In a dual damascene process, both the via and trenches are etched in the dielectric layer overlying an underlying interconnect or trace. The desired metal is then deposited into the trenches and holes in one step to form a dual damascene structure. Chemical mechanical polishing (CMP) is used to remove the unwanted surface metal, while leaving the desired metal in the trenches and holes, thus forming in-laid interconnect lines and vias that are coupled to electrical components beneath the insulation layer. The CMP processing leaves a planarized surface for subsequent metallization to build multi-level interconnections.
The introduction of copper conductors in integrated circuits has received wide publicity. Copper interconnect is the most promising metallization scheme for future generation high-speed ULSI, primarily because of lower electrical resistivity (1.7 vs. 2.3 μΩcm) and more electro/stress-migration resistance than the conventional aluminum-based materials. Full, 6-level copper wiring has now been introduced in a sub-0.25 μm CMOS ULSI technology. However, copper atoms can easily diffuse through most oxides into the devices in the underlying silicon substrate and act as recombination centers to spoil device performance. Copper also diffuses into commonly used dielectric materials (i.e., SiO2) and certain polymers, resulting in conductivity of these insulators and higher effective dielectric constants.
Based on the foregoing, a suitable diffusion barrier is needed in order to adopt copper interconnects for ULSI. A variety of barrier materials such as tantalum (Ta), tantalum silicon nitride (TaSiN), titanium nitride (TiN), tantalum nitride (TaN) and tungsten nitride (WN) have been investigated.
These barrier films are generally deposited by sputtering to a thickness range of 20 to 30 nm and higher. If the barrier thickness does not scale with the device (and wiring scaling), the impact on electrical resistance is significant. The resistance increase due to liner (diffusion barrier) thickness becomes substantial for line widths of approximately 0.2 μm and below. It has been reported that a very thin (<6 nm) tungsten silicon nitride (WSiN) layer formed by electron cyclotron resonance (ECR) plasma nitridation of sputtered WSi film prevented copper diffusion.
A barrier metal free copper damascene interconnection technology has been reported. The scheme involved formation of a thin barrier layer on the surface of silicon oxyfluoride (SiOF) film by ammonia (NH3) plasma treatment. The reflow of copper was then performed at 400° C. in atmospheric gas composed of N2/H2.
It would be desirable to provide a process for the formation of conductive contacts and interconnect lines that eliminates the need for depositing a metal barrier diffusion layer and results in a conductive contact/interconnect that has a higher purity and a lower resistivity compared to prior art films and contact structures.